SuccessConsole Output

Triggered by Gerrit: http://ci.csn.khai.edu/gerrit/1476
Building on master in workspace /var/jenkins_home/workspace/vhdl-linter
Wiping out workspace first.
Cloning the remote Git repository
Cloning repository https://ci.csn.khai.edu/gerrit/alekseenko/dtcs
 > git init /var/jenkins_home/workspace/vhdl-linter/src # timeout=10
Fetching upstream changes from https://ci.csn.khai.edu/gerrit/alekseenko/dtcs
 > git --version # timeout=10
 > git fetch --tags --progress https://ci.csn.khai.edu/gerrit/alekseenko/dtcs +refs/heads/*:refs/remotes/origin/*
 > git config remote.origin.url https://ci.csn.khai.edu/gerrit/alekseenko/dtcs # timeout=10
 > git config --add remote.origin.fetch +refs/heads/*:refs/remotes/origin/* # timeout=10
 > git config remote.origin.url https://ci.csn.khai.edu/gerrit/alekseenko/dtcs # timeout=10
Fetching upstream changes from https://ci.csn.khai.edu/gerrit/alekseenko/dtcs
 > git fetch --tags --progress https://ci.csn.khai.edu/gerrit/alekseenko/dtcs refs/changes/*:refs/changes/*
 > git rev-parse refs/changes/76/1476/5^{commit} # timeout=10
 > git rev-parse refs/remotes/origin/refs/changes/76/1476/5^{commit} # timeout=10
JENKINS-19022: warning: possible memory leak due to Git plugin usage; see: https://wiki.jenkins-ci.org/display/JENKINS/Remove+Git+Plugin+BuildsByBranch+BuildData
Checking out Revision 066445b66524d15a45fb5adc4c91b3d34ebeac5a (refs/changes/76/1476/5)
 > git config core.sparsecheckout # timeout=10
 > git checkout -f 066445b66524d15a45fb5adc4c91b3d34ebeac5a
Commit message: "lab4"
First time build. Skipping changelog.
[vhdl-linter] $ /bin/sh -xe /tmp/jenkins8821762753491094512.sh
+ cd src
+ git clone https://gist.github.com/d1acee9fd68388636c50a4349abfa72b.git bakalint
Cloning into 'bakalint'...
+ find . -name *.vhd -print0
+ xargs -0 -I {} perl bakalint/bakalint.pl --input={} --no-header
./lab_3_1_tb.vhd:1:information - wrong case [ieee].
./lab_3_1_tb.vhd:2:information - wrong case [ieee].
./lab_3_1_tb.vhd:4:information - use mixed case for entities [lab_3_1_tb].
./lab_3_1_tb.vhd:4:information - choosing Lab_3_1_tb as replacement.
./lab_3_1_tb.vhd:7:information - use mixed case for architectures [rtl].
./lab_3_1_tb.vhd:7:information - choosing Rtl as replacement.
./lab_3_1_tb.vhd:8:information - use mixed case for components [lab_3_1].
./lab_3_1_tb.vhd:8:information - choosing Lab_3_1 as replacement.
./lab_3_1_tb.vhd:23:information - label and sentence in the same line.
./lab_3_1_tb.vhd:33:information - label and sentence in the same line.
./lab_3_1_tb.vhd:39:information - label and sentence in the same line.
End of ./lab_3_1_tb.vhd
./comp_lab_3.vhd:1:information - wrong case [ieee].
./comp_lab_3.vhd:2:information - wrong case [ieee].
./comp_lab_3.vhd:3:information - wrong case [ALL].
./comp_lab_3.vhd:5:information - use mixed case for entities [comp_lab_3].
./comp_lab_3.vhd:5:information - choosing Comp_lab_3 as replacement.
./comp_lab_3.vhd:14:information - use mixed case for architectures [compon_1].
./comp_lab_3.vhd:14:information - choosing Compon_1 as replacement.
./comp_lab_3.vhd:16:information - use mixed case for components [t_trigger].
./comp_lab_3.vhd:16:information - choosing T_trigger as replacement.
./comp_lab_3.vhd:36:information - label and sentence in the same line.
./comp_lab_3.vhd:37:information - label and sentence in the same line.
./comp_lab_3.vhd:38:information - label and sentence in the same line.
./comp_lab_3.vhd:39:information - label and sentence in the same line.
./comp_lab_3.vhd:40:information - label and sentence in the same line.
./comp_lab_3.vhd:41:information - label and sentence in the same line.
End of ./comp_lab_3.vhd
End of ./Vhdl2.vhd
./plus_one.vhd:1:information - wrong case [ieee].
./plus_one.vhd:2:information - wrong case [ieee].
./plus_one.vhd:3:information - wrong case [ALL].
./plus_one.vhd:5:information - use mixed case for entities [plus_one].
./plus_one.vhd:5:information - choosing Plus_one as replacement.
./plus_one.vhd:13:information - use mixed case for architectures [plus_one_tt].
./plus_one.vhd:13:information - choosing Plus_one_tt as replacement.
End of ./plus_one.vhd
./t_trigger.vhd:1:information - wrong case [ieee].
./t_trigger.vhd:2:information - wrong case [ieee].
./t_trigger.vhd:4:information - use mixed case for entities [t_trigger].
./t_trigger.vhd:4:information - choosing T_trigger as replacement.
./t_trigger.vhd:14:information - use mixed case for architectures [beh_t_trigger].
./t_trigger.vhd:14:information - choosing Beh_t_trigger as replacement.
./t_trigger.vhd:17:information - label and sentence in the same line.
End of ./t_trigger.vhd
./comp_lab_3_tb.vhd:1:information - wrong case [ieee].
./comp_lab_3_tb.vhd:2:information - wrong case [ieee].
./comp_lab_3_tb.vhd:4:information - use mixed case for entities [comp_lab_3_tb].
./comp_lab_3_tb.vhd:4:information - choosing Comp_lab_3_tb as replacement.
./comp_lab_3_tb.vhd:8:information - use mixed case for architectures [rtl].
./comp_lab_3_tb.vhd:8:information - choosing Rtl as replacement.
./comp_lab_3_tb.vhd:9:information - use mixed case for components [comp_lab_3].
./comp_lab_3_tb.vhd:9:information - choosing Comp_lab_3 as replacement.
./comp_lab_3_tb.vhd:22:information - label and sentence in the same line.
./comp_lab_3_tb.vhd:29:information - label and sentence in the same line.
End of ./comp_lab_3_tb.vhd
./lab_3_1.vhd:1:information - wrong case [ieee].
./lab_3_1.vhd:2:information - wrong case [ieee].
./lab_3_1.vhd:3:information - wrong case [ALL].
./lab_3_1.vhd:5:information - use mixed case for entities [lab_3_1].
./lab_3_1.vhd:5:information - choosing Lab_3_1 as replacement.
./lab_3_1.vhd:15:information - use mixed case for architectures [rtl].
./lab_3_1.vhd:15:information - choosing Rtl as replacement.
./lab_3_1.vhd:17:information - label and sentence in the same line.
End of ./lab_3_1.vhd
./forg.vhd:1:information - wrong case [ieee].
./forg.vhd:2:information - wrong case [ieee].
./forg.vhd:3:information - wrong case [ALL].
./forg.vhd:5:information - use mixed case for entities [forg].
./forg.vhd:5:information - choosing Forg as replacement.
./forg.vhd:13:information - use mixed case for architectures [struct1].
./forg.vhd:13:information - choosing Struct1 as replacement.
./forg.vhd:14:information - use mixed case for components [t_trigger].
./forg.vhd:14:information - choosing T_trigger as replacement.
./forg.vhd:24:information - wrong case [Left].
./forg.vhd:25:information - wrong case [Left].
./forg.vhd:28:information - wrong case [Left].
./forg.vhd:28:information - label and sentence in the same line.
./forg.vhd:29:information - label and sentence in the same line.
./forg.vhd:32:information - label and sentence in the same line.
./forg.vhd:35:information - wrong case [Left].
./forg.vhd:39:information - label and sentence in the same line.
End of ./forg.vhd
./forg_tb.vhd:1:information - wrong case [ieee].
./forg_tb.vhd:2:information - wrong case [ieee].
./forg_tb.vhd:4:information - use mixed case for entities [forg_tb].
./forg_tb.vhd:4:information - choosing Forg_tb as replacement.
./forg_tb.vhd:7:information - use mixed case for architectures [rtl].
./forg_tb.vhd:7:information - choosing Rtl as replacement.
./forg_tb.vhd:8:information - use mixed case for components [forg].
./forg_tb.vhd:8:information - choosing Forg as replacement.
./forg_tb.vhd:24:information - label and sentence in the same line.
End of ./forg_tb.vhd
Finished: SUCCESS