FailedConsole Output

Triggered by Gerrit: http://ci.csn.khai.edu/gerrit/1259
Building on master in workspace /var/jenkins_home/workspace/vhdl-linter
Wiping out workspace first.
Cloning the remote Git repository
Cloning repository https://ci.csn.khai.edu/gerrit/alekseenko/dtcs
 > git init /var/jenkins_home/workspace/vhdl-linter/src # timeout=10
Fetching upstream changes from https://ci.csn.khai.edu/gerrit/alekseenko/dtcs
 > git --version # timeout=10
 > git fetch --tags --progress https://ci.csn.khai.edu/gerrit/alekseenko/dtcs +refs/heads/*:refs/remotes/origin/*
 > git config remote.origin.url https://ci.csn.khai.edu/gerrit/alekseenko/dtcs # timeout=10
 > git config --add remote.origin.fetch +refs/heads/*:refs/remotes/origin/* # timeout=10
 > git config remote.origin.url https://ci.csn.khai.edu/gerrit/alekseenko/dtcs # timeout=10
Fetching upstream changes from https://ci.csn.khai.edu/gerrit/alekseenko/dtcs
 > git fetch --tags --progress https://ci.csn.khai.edu/gerrit/alekseenko/dtcs refs/changes/*:refs/changes/*
 > git rev-parse refs/changes/59/1259/2^{commit} # timeout=10
 > git rev-parse refs/remotes/origin/refs/changes/59/1259/2^{commit} # timeout=10
JENKINS-19022: warning: possible memory leak due to Git plugin usage; see: https://wiki.jenkins-ci.org/display/JENKINS/Remove+Git+Plugin+BuildsByBranch+BuildData
Checking out Revision 7e570c26a2b345268ab7374ce523ac5c8d42ed1f (refs/changes/59/1259/2)
 > git config core.sparsecheckout # timeout=10
 > git checkout -f 7e570c26a2b345268ab7374ce523ac5c8d42ed1f
Commit message: "lab3"
First time build. Skipping changelog.
[vhdl-linter] $ /bin/sh -xe /tmp/jenkins6588457763497992732.sh
+ cd src
+ git clone https://gist.github.com/d1acee9fd68388636c50a4349abfa72b.git bakalint
Cloning into 'bakalint'...
+ find . -name *.vhd -print0+ 
xargs -0 -I {} perl bakalint/bakalint.pl --input={} --no-header
./Lab3_TPKS_tb.vhd:1:information - wrong case [ieee].
./Lab3_TPKS_tb.vhd:2:information - wrong case [ieee].
./Lab3_TPKS_tb.vhd:6:information - use mixed case for architectures [rtl].
./Lab3_TPKS_tb.vhd:6:information - choosing Rtl as replacement.
./Lab3_TPKS_tb.vhd:9:information - rename `a` to `a_i`.
./Lab3_TPKS_tb.vhd:10:information - rename `b` to `b_i`.
./Lab3_TPKS_tb.vhd:11:information - rename `c` to `c_i`.
./Lab3_TPKS_tb.vhd:12:information - rename `res1` to `res1_o`.
./Lab3_TPKS_tb.vhd:21:information - label and sentence in the same line.
./Lab3_TPKS_tb.vhd:31:information - label and sentence in the same line.
./Lab3_TPKS_tb.vhd:41:information - label and sentence in the same line.
End of ./Lab3_TPKS_tb.vhd
./Lab3_TPKS.vhd:2:information - wrong case [ALL].
./Lab3_TPKS.vhd:3:information - wrong case [ALL].
./Lab3_TPKS.vhd:7:information - rename `a` to `a_i`.
./Lab3_TPKS.vhd:8:information - rename `b` to `b_i`.
./Lab3_TPKS.vhd:9:information - rename `c` to `c_i`.
./Lab3_TPKS.vhd:10:information - rename `res1` to `res1_o`.
./Lab3_TPKS.vhd:14:information - use mixed case for architectures [rtl].
./Lab3_TPKS.vhd:14:information - choosing Rtl as replacement.
./Lab3_TPKS.vhd:16:information - label and sentence in the same line.
End of ./Lab3_TPKS.vhd
./Lab04_TPKS_tb.vhd:1:information - wrong case [ieee].
./Lab04_TPKS_tb.vhd:2:information - wrong case [ieee].
./Lab04_TPKS_tb.vhd:8:information - use mixed case for architectures [rtl].
./Lab04_TPKS_tb.vhd:8:information - choosing Rtl as replacement.
./Lab04_TPKS_tb.vhd:11:information - rename `r` to `r_i`.
./Lab04_TPKS_tb.vhd:12:information - rename `s` to `s_i`.
./Lab04_TPKS_tb.vhd:13:information - rename `l` to `l_i`.
./Lab04_TPKS_tb.vhd:14:error - use lower case for ports [cLK].
./Lab04_TPKS_tb.vhd:14:information - rename `clk` to `clk_i`.
./Lab04_TPKS_tb.vhd:15:information - rename `q` to `q_o`.
./Lab04_TPKS_tb.vhd:25:information - label and sentence in the same line.
./Lab04_TPKS_tb.vhd:33:information - label and sentence in the same line.
./Lab04_TPKS_tb.vhd:41:information - label and sentence in the same line.
./Lab04_TPKS_tb.vhd:49:information - label and sentence in the same line.
End of ./Lab04_TPKS_tb.vhd
Found 1 error.
I suggest the changes found in `./Lab04_TPKS_tb.lint.vhdl` output file.
The corrected file is most probably wrong.
./Lab04_TPKS.vhd:1:information - wrong case [ieee].
./Lab04_TPKS.vhd:2:information - wrong case [ieee].
./Lab04_TPKS.vhd:6:information - rename `r` to `r_i`.
./Lab04_TPKS.vhd:7:information - rename `s` to `s_i`.
./Lab04_TPKS.vhd:8:information - rename `l` to `l_i`.
./Lab04_TPKS.vhd:9:error - use lower case for ports [cLK].
./Lab04_TPKS.vhd:9:information - rename `clk` to `clk_i`.
./Lab04_TPKS.vhd:10:information - rename `q` to `q_o`.
./Lab04_TPKS.vhd:15:information - use mixed case for architectures [rtl].
./Lab04_TPKS.vhd:15:information - choosing Rtl as replacement.
./Lab04_TPKS.vhd:17:information - label and sentence in the same line.
End of ./Lab04_TPKS.vhd
Found 1 error.
I suggest the changes found in `./Lab04_TPKS.lint.vhdl` output file.
The corrected file is most probably wrong.
Build step 'Execute shell' marked build as failure
Finished: FAILURE